1. Field of the Invention
The present invention relates generally to a random access semiconductor memory (RAM) device, and more particularly to an improvement of column selection of a memory cell array.
2. Description of the Related Art
FIG. 6 shows part of a structure of a memory core portion of a conventional general purpose DRAM.
In the memory core portion, memory cells 10 are arranged in a matrix, forming a memory cell array. A sense amplifier 11 is connected to a pair of bit lines in each column of the cell array. The pair of bit lines (21, 22; 23, 24; . . . ) in each column is connected to a pair of common input/output data lines via a corresponding pair of column selection gates. Column decoders 12 are connected to the respective columns. The pair of column selection gates (31, 32; 33, 34; . . . ) in each column is controlled by an output of a corresponding column decoder 12. As a result, each column can be selected by an output of the corresponding column decoder both in writing and reading operations.
A conventional random access semiconductor memory, such as the aforementioned DRAM, has an architecture in which the number of column decoders is the same as that of column addresses, so that the same number of columns can be selected in both reading and writing operations.
A computer system in recent years tends to be formed as a so-called "system on chip", wherein a memory portion and a data processing function portion are mounted on the same semiconductor chip. When the "system on chip" is improved such that the memory itself has the data processing function portion or that an exclusive memory for a limited purpose is to be realized, a new architecture different from the above-described conventional architecture may be introduced with regard to selection of a column of the memory cell array, in which case, the number of columns selected in a reading operation can be different from the number of columns selected in a writing operation.
FIG. 7 shows a structure of a memory core portion in a case where an architecture, in which the numbers of selected columns are different in the reading and writing operations, is applied to a conventional DRAM having column decoders of a number which coincides with the number of column addresses.
The memory core portion has two pairs of input/output data lines (41, 42 and 43, 44) so that data of two bits can be simultaneously read. More specifically, the pair of bit lines of an odd column is connected to a first pair of input/output data lines (41 and 42) via a corresponding pair of column selection gates, while the pair of bit lines of an even column is connected to a second input/output data lines (43 and 44) via a corresponding pair of column selection gates. The memory core portion further includes a gate circuit comprising a two-input OR gate 13 and a two-input AND gate 14, which corresponds to a pair of column selection gates (31, 32; 33, 34; . . . ) in each column.
An output of the corresponding column decoder 12 is input to one input of each of the two-input OR gates 13 and an output of the corresponding two-input AND gate 14 is input to the other input of the gate 13. A write enable signal (/WE) is input to one input of each of the two-input AND gates 14 and an output of a column decoder (for example, "i+1"th) adjacent to the corresponding column decoder 12 ("i"th) is input to the other input of the gate 14.
In the above structure, during a writing operation, the signal/ WE is "L" level, with the result that the output of the AND gate 14 in each column becomes "L" level. When an output of the column decoder 12 becomes "H" level, an output of the two-input OR gate 13 becomes "H" level, thereby turning on a pair of column selection gates, so that the corresponding column is selected. As a result, data is input to the selected column via the pair of input/output data lines (41, 42; or 43, 44), so that 1 bit data can be written in the memory cell of the column.
During a reading operation, the signal/ WE is "H" level. An output from the gate of each column is "H" level, when an input from a column decoder 12 adjacent to the corresponding column decoder of the column decoder row is "H" level. Therefore, one column can be selected not only when an output of the corresponding column decoder (e.g., i) becomes "H" level and an output of the corresponding two-input OR gate 13 becomes "H" level, so that the corresponding pair of column selection gates 31 and 32 can be turned on, but also when an output of the adjacent column decoder (i+1) becomes "H" level and an output of the corresponding two-input 0R gate 13 becomes "H" level, thereby turning on the corresponding pair of column selection gates 31 and 32.
In other words, in a reading operation, when an output of a column decoder 12 becomes "H" level, the corresponding column and a column corresponding to an adjacent column decoder are simultaneously selected. Hence, data of two bits are read through the two pairs of input/output data lines (41, 42; 43, 44).
The above system, in which two columns are accessed by means of a logical OR between outputs of two adjacent column decoders of the column decoders 12 of the same number as the number of column addresses, is called a two-column access system. When this system is to be employed in a memory device, only one column can be selected by an output of the corresponding one column decoder 12 in a column located at an end of the memory cell array (or a sub-array in a case where the array is divided into a plurality of blocks). This system is thus disadvantageous in that data of two bits cannot be read simultaneously.
As shown in FIG. 8, as regards a column located at an end (for example, the rightmost column in the drawing), i.e., the column corresponding to the most significant bit of the column address, although this column includes a column decoder (N), there is not column decoder adjacent thereto in the column decoder row (on the right side thereof in the drawing). Accordingly, it is impossible to arrange a logical gate so that the column can be selected when an output from the adjacent column decoder is "H" level. Hence, when the most significant column is designated in a reading operation, since only the most significant column is selected, data of only one bit can be read.
To solve this problem, it is proposed to constitute a memory device such that a column at an end of the memory cell array can be accessed by means of a logical OR between outputs from the two column decoders in the columns located both ends of the memory cell array, i.e., the two column decoders at both ends of the column decoder row.
In this case, however, it is necessary to arrange a long signal line for supplying an output from the column decoder at an end of the column decoder row to an input node of the logical gate of an output side of the column decoder at the other end of the column decoder row. This long signal line may cause a problem of a signal delay.
In addition, since the long signal line has a great parasitic capacitance, the column decoder which supplies an output to the signal line must have a greater driving capacity than the other column decoders. Therefore, the column decoders cannot be arranged in a regular pattern. Moreover, when the aforementioned signal line is arranged, the pattern layout of the column decoder row is inevitably limited.
As described above, in the conventional semiconductor memory device wherein the number of column decoders is the same as the number of columns, if an additional column is to be selected by a logical 0R between outputs from a plurality of column decoders in order to access a plurality of columns simultaneously, a column located at an end of the memory cell array can be selected only by an output of the corresponding column decoder, i.e., only one column can be selected. Therefore, it is difficult to achieve a system in which a plurality of columns can be simultaneously accessed.